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SOI technology has taken power/performance benefits of CMOS beyond those of bulk-CMOS technology in the arena of high-performance applications, including 4.7 GHz dual core Power 6 IC, PowerPC, and game processors. At the 45 nm node we have expanded the menu of devices offered in SOI technology to include general purpose applications, including ASICs and low power products. A spectrum of memory solutions,...
NXP offers a wide range of smart power technologies. Where the SOI based A-BCD (Advanced Bipolar, CMOS, DMOS) technology is maturalised and widely used in cars, lamps and audio amplifiers.
In this paper we will present two applications: high temperature electronics where SOI has a monopole for temperature between 200degC and 300degC and RF electronics where SOI has interesting performances compare to bulk. SOI is an enabling technology for high temperatures with an easier design technique. There are several SOI processes dedicated to RF applications and their main advantage will be...
We demonstrate NMOS performance enhancements of up to ~18% for applications in a 45 nm SOI technology. The performance boost was achieved using high tensile-stressed UV film in conjunction with stress memorization techniques (SMT). For the first time we demonstrate that using a UV-cured tensile film allows a 6% performance boost on the SOI NMOS, achieving a drive current of ~1170 muA/mum (1250, non-self-heated)...
We report a CMOS-compatible embedded silicon-carbon (eSiC) source/drain stressor technology with NMOS performance enhancement. The integration includes up to 2.6% substitutional carbon (Csub) epitaxial Si:C and laser spike annealing (LSA) for increased Csub incorporation. 26% channel resistance (Rch) reduction and 11% Idlin-Ioff enhancement for 0.5% Csub and 60% Rch reduction for 2.2% Csub are demonstrated.
In this paper, we report for the first time electrical performances of high hole mobility pMOSFETs with high-k/metal gate using ultra-thin GeOI wafers as templates obtained by the Ge condensation technique. It is concluded that the results coupled with a localized Ge condensation technique, open the way to planar SOI-nMOSFET/GeOI-pMOSFET co-integration.
This paper presents a detailed study of SOI source/drain embedded SiGe (eSiGe) technology with a focus on parasitic characteristics. It shows that eSiGe can appreciably suppress on-state floating body effect and improve device exterior resistance. Although eSiGe only physically addresses P-FET, junction capacitances of both P- and N-FETs can be impacted.
In this paper, simultaneous NMOS drive current enhancement and gate leakage reduction via a novel silicon superlattice on SOI high mobility channel replacement layer is demonstrated. The technology, which is termed MST-SOI, has demonstrated in excess of 20% mobility enhancement, up to 30% drive current enhancement and significant gate leakage reduction compared to a baseline SOI process.
We develop, for the first time, a compact and scalable model to account for the poly-space effects (PSEs) in uniaxially-strained etch stop layer (ESL) stressors. The model is based on 2-dimensional (2D) finite element (FEM) stress simulations and 4-point bending characterization of silicon, and agrees well with measured data. The impact of PSEs on circuit performance is also discussed.
This paper reviews MuGFET (multi-gate MOSFET) devices performance under extreme temperature range (5-573 K) and total radiation dose up to 6 Mrad. It is concluded that MuGFET is not only a good platform for CMOS scaling, but also an excellent platform for operation in harsh environments.
We have demonstrated NMOS FinFET devices with a Vt of 0.33V through As implantation into TiN. The method allows for multiple Vt FinFET devices with Vt's of 0.33V, 0.55V (NMOS) and -0.35V (PMOS) through just one As implantation step into lOnm TiN. The NMOS Vt can be further modulated by adjusting the As implantation dose. Further optimization of the cap, implantation and annealing conditions will be...
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